1. Field of the Invention
This invention relates to an electrically reprogrammable non-volatile semiconductor memory device. Especially this invention relates to the voltage supply technology of a memory cell in a NAND type flash memory (a kind of a non-volatile semiconductor memory device).
2. Description of Related Art
Recently, the demand of nonvolatile semiconductor memory which is high density and large capacity is increasing in accordance with the growth of the application like silicon audio, digital still camera, and so on. Such applications require not only greater storage capacity but also higher program throughput. NAND flash memory meets those requirements, because of the small cell size and both the program operation and an erasure operation by using FN tunnel current. The memory cell size is about 4F2 (F is design feature size) formed in the intersection of the active region of Si, and the line pattern of a control gate. Therefore, compared with other nonvolatile memory, high integration of a memory cell can be realized. However, since the NAND flash memory retains data in nonvolatile manner with the amount of electric charges in a floating gate, shrinkage of the thickness of the tunnel oxide film is difficult. Thus, the voltages required for the program operation and the erase operation are retained, although high integration is progressed.
In a NAND type flash memory, the voltage beyond 20V is applied to selection gates of selection transistors, and control gates of memory cells in program operation or an erase operation. Therefore, high voltage tolerance transistors having thick gate oxide, sufficient junction voltage tolerance, and sufficient voltage tolerance between elements is used for transmission transistors for supplying signals to selection gate lines and word lines. Because of this situation, it will be necessary to arrange large transfer transistors in each block selection circuit, the transistor being larger than transistors which operates with the usual supply voltage. And the increase in efficiency of layout arrangement of the transistor is called for.
Adopting a layout configuration pattern without separation of gate patterns is known so that it may be indicated by the patent documents 1 (Japanese laid open patent 2002-141477). Moreover, by adopting how to put in order the transfer transistor which can make distance between transistors as small as possible, the technology which makes occupancy area of a block selection circuit as small as possible is known.